SH7727 Datasheet, PDF(709/1109 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7727 Datasheet, PDF (709/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

◁

Section 20 Serial IO (SIOF)

20.3.5 Control Data Interface

Control data outputs the control command to CODEC and receive the state of CODEC. SIOF

support the following two operations as an interface operation of control data.

â¢ Control by the slot positions

â¢ Control by secondary FS

Control data is effective when selecting 16 bit as data length and MSB first receive mode.

(1) Control by Slot Positions (Master Mode 1)

This is the method that dedicates the slot passion of control data in a frame to transmit or receive

the control data.

Figure 20.7 shows a sample of control data interface timing by slot position.

Note: When using this method, peripheral clock (PÏ) should be used as the master clock (Master

Clock Select (MSSEL) = 1).

1 frame

SCK_SIO

SIOFSYN

TXD_SIO

RXD_SIO

Lch. DATA Control ch.0 Rch. DATA Control ch.1

â

Slot No.0 Slot No.1 Slot No.2 Slot No.3

Setting: TRMD = 00 or 10, REDG = 0,

TDLE = 1,

TDLA3 to TDLA0 = 0000,

RDLE = 1,

RDLA3 to RDLA0 = 0000,

CD0E = 1,

CD0A3 to CD0A0 = 0001,

FL = (frame length 128 bits),

TDRE = 1,

TDRA3 to TDRA0 = 0010,

RDRE = 1,

RDRA3 to RDRA0 = 0010,

CD1E = 1,

CD1A3 to CD1A0 = 0011

Figure 20.7 Control Data Interface (Slot Position)

Rev. 5.00 Dec 12, 2005 page 637 of 1034

REJ09B0254-0500

▷