SH7727 Datasheet, PDF (638/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
• The quantity of data in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be known.
• The time-out error (DR) can be detected in receiving.
19.1.2 Block Diagram
Figure 19.1 shows a block diagram of the SCIF.
Module data bus
Internal
data bus
SCFRDR2 SCFTDR2
(16stages) (16stages)
SCPCR2
SCFDR2
SCFDR2
SCFCR2
SCBRR2
SCSSR2
RxD2
TxD2
SCRSR2
SCTSR2
SCSCR2
SCSMR2
Transmit/
receive
control
Parity generation
Baud rate
generator
Clock
Pφ
Pφ/4
Pφ/16
Pφ/64
RTS2
CTS2
Parity check
ERI
TXI
BRI
BRI
SCIF
Legend:
SCRSR2: Receive shift register 2
SCFRDR2: Receive FIFO data register 2
SCTSR2: Transmit shift register 2
SCFTDR2: Transmit FIFO data register 2
SCSMR2: Serial mode register 2
SCSCR2: Serial control register 2
SCSSR2: Serial status register 2
SCBRR2: Bit rate register 2
SCFCR2: FIFO control register 2
SCFDR2: FIFO data count set register 2
SCPDR2: Port SC data register 2
SCPCR2: Port SC control register 2
Figure 19.1 SCIF Block Diagram
Rev. 5.00 Dec 12, 2005 page 566 of 1034
REJ09B0254-0500