SH7727 Datasheet, PDF (236/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 6 X/Y Memory
Area 1, 64 Mbytes
4000000
I/O register space
16 Mbytes
5000000
5020000
X/Y Memory
6000000
Reserved
space
16 Mbytes
Reserved area
32 Mbytes
128-kbyte X/Y Memory
A5000000
X-ROM/X-RAM
Reserved space
A5007000
A5008FFF
X-RAM, 8 kbytes
A5010000
X-ROM/X-RAM
Reserved space
Y-ROM/Y-RAM
Reserved space
A5017000
Y-RAM, 8 kbytes
A5018FFF
7FFFFFF
A501FFFF
Y-ROM/Y-RAM
Reserved space
Figure 6.2 X/Y Memory Physical Address Mapping
6.3 X/Y Memory Access from the DSP
The X/Y memory can be accessed by the DSP through the X bus and Y bus. Accesses via the X
bus/Y bus are always 16-bit, while accesses via the L bus are either 16-bit or 32-bit. Accesses via
the X bus and Y bus cannot be specified simultaneously.
6.4 X/Y Memory Access from the DMAC
The X/Y memory also exists on the I bus and can be accessed by the DMAC. The DMAC access
is 8-/16-/32-bit unit. If the I bus accesses X/Y memory simultaneously with an access from X
bus/Y bus or L bus, the I bus master has a higher priority.
To access the X/Y memory by the DMAC, the physical address from H’05000000 to H’0501FFFF
should be used.
Rev. 5.00 Dec 12, 2005 page 164 of 1034
REJ09B0254-0500