SH7727 Datasheet, PDF (46/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

23.5.8 USB Interrupt Flag Register 1 (USBIFR1) .......................................................... 697
23.5.9 USB Trigger Register (USBTRG) ....................................................................... 698
23.5.10 USBFIFO Clear Register (USBFCLR) ................................................................ 699
23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) ....................................... 699
23.5.12 USB Data Status Register (USBDASTS) ............................................................ 700
23.5.13 USB Endpoint Stall Register (USBEPSTL) ........................................................ 700
23.5.14 USB Interrupt Enable Register 0 (USBIER0)...................................................... 701
23.5.15 USB Interrupt Enable Register 1 (USBIER1)...................................................... 701
23.5.16 USBEP1 Receive Data Size Register (USBEPSZ1) ............................................ 701
23.5.17 USB Interrupt Select Register 0 (USBISR0) ....................................................... 702
23.5.18 USB Interrupt Select Register 1 (USBISR1) ....................................................... 702
23.5.19 USBDMA Setting Register (USBDMAR)........................................................... 703
23.6 Operation........................................................................................................................... 704
23.6.1 Cable Connection................................................................................................. 704
23.6.2 Cable Disconnection ............................................................................................ 705
23.6.3 Control Transfer................................................................................................... 706
23.6.4 EP1 Bulk-Out Transfer (Dual FIFOs).................................................................. 713
23.6.5 EP2 Bulk-In Transfer (Dual FIFOs) .................................................................... 714
23.6.6 EP3 Interrupt-In Transfer..................................................................................... 716
23.7 Processing of USB Standard Commands and Class/Vendor Commands.......................... 717
23.7.1 Processing of Commands Transmitted by Control Transfer ................................ 717
23.8 Stall Operations................................................................................................................. 718
23.8.1 Overview.............................................................................................................. 718
23.8.2 Forcible Stall by Application ............................................................................... 718
23.8.3 Automatic Stall by USB Function Module .......................................................... 720
23.9 Usage Notes ...................................................................................................................... 722
23.9.1 Receiving Setup Data........................................................................................... 722
23.9.2 Clearing the FIFO ................................................................................................ 722
23.9.3 Overreading and Overwriting the Data Registers ................................................ 722
23.9.4 Assigning Interrupt Sources to EP0 ..................................................................... 723
23.9.5 Clearing the FIFO when DMA Transfer Is Enabled ............................................ 723
23.9.6 Notes on TR Interrupt .......................................................................................... 723
23.9.7 Peripheral Clock (Pφ) Operation Frequency ........................................................ 724
Section 24 USB HOST Module ...................................................................................... 725
24.1 General Description .......................................................................................................... 725
24.1.1 Features................................................................................................................ 725
24.1.2 Pin Configuration................................................................................................. 726
24.1.3 Register Configuration......................................................................................... 727
24.2 Register Description.......................................................................................................... 728
24.2.1 HcRevision........................................................................................................... 728
Rev. 5.00 Dec 12, 2005 page xlvi of lxxii