SH7727 Datasheet, PDF (371/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 2n + 1, 2n—Area n (6 to 2, 0) Intercycle Idle Specification (AnIW1, AnIW0): Specify the
number of idles inserted between bus cycles when switching between physical space area n (6 to
2, 0) to another space or between a read access to a write access in the same physical space.
Bit 2n + 1: AnIW1
0
1
Bit 2n: AnIW0
0
1
0
1
Description
1 idle cycle inserted
1 idle cycle inserted
2 idle cycles inserted
3 idle cycles inserted (Initial value)
12.2.4 Wait State Control Register 2 (WCR2)
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
A6 A6 A6 A5 A5 A5 A4 A4 A4 A3 A3 A2 A2 A0 A0 A0
W2 W1 W0 W2 W1 W0 W2 W1 W0 W1 W0 W1 W0 W2 W1 W0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Dec 12, 2005 page 299 of 1034
REJ09B0254-0500