SH7727 Datasheet, PDF (26/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Page
Previous Version
942 Table 32.6 Control Signal Timing
RESETP pulse width
RESETP setup time^*1
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
NMI setup time ^*1
NMI hold time
IRQ5–IRQ0 setup time ^*1
IRQ5–IRQ0 hold time
BACK delay time
STATUS1, STATUS0 delay
time
Bus tri-state delay time 1
Bus tri-state delay time 2
Bus buffer-on time 1
Bus buffer-on time 2
tRESPW
tRESPS
tRESPH
tRESMW
tRESMS
tRESMH
tBREQS
tBREQH
tNMIS
tNMIH
tIRQS
tIRQH
tBACKD
tSTD
33 MHz^*2
Min Max
20
—
23
—
2
—
12
—
3
—
34
—
10
—
3
—
10
—
4
—
10
—
4
—
—
10
—
16
tBOFF1 0
15
tBOFF2 0
15
tBON1
0
15
tBON2
0
15
66.67 MHz^*3
Min
20^*4
Max
—
23
—
2
—
12^*5 —
3
—
34
—
10
—
3
—
10
—
4
—
10
—
4
—
—
10
—
16
0
15
0
15
0
15
0
15
Notes:
*1 RESETP, NMI and IRQ5 to IRQ0 are
asynchronous. Changes are detected at
the clock fall when the setup shown is
used. When the setup cannot be used,
detection can be delayed until the next
clock falls. When using as IRL, please
observe the setup time.
*2 When Vcc = 1.6 to 2.05 V and VccQ =
2.6 to 3.6 V, the upper limit of the external
bus clock is 33 MHz.
*3 When Vcc = 1.75 to 2.05 V and VccQ =
3.0 to 3.6 V, the upper limit of the external
bus clock is 66.67 MHz.
*4 In the standby mode, tRESPW = tOSC2 (10
ms). In the sleep mode, tRESPW = tPLL1 (100
µs). When the clock multiplication ratio is
changed, tRESPW = tPLL1 (100 µs).
Revised Version
Table 32.9 Control Signal Timing
RESETP pulse width
RESETP setup time^*1
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
NMI setup time ^*1
NMI hold time
IRQ5–IRQ0 setup time ^*1
IRQ5–IRQ0 hold time
BACK delay time
STATUS1, STATUS0 delay time
Bus tri-state delay time 1
Bus tri-state delay time 2
Bus buffer-on time 1
Bus buffer-on time 2
tRESPW
tRESPS
tRESPH
tRESMW
tRESMS
tRESMH
tBREQS
tBREQH
tNMIS
tNMIH
tIRQS
tIRQH
tBACKD
tSTD
tBOFF1
tBOFF2
tBON1
tBON2
Min
20^*2
23
2
12^*3
3
34
10
3
10
4
10
4
—
—
0
0
0
0
Max
—
—
—
—
—
—
—
—
—
—
—
—
10
16
15
15
15
15
1. RESETP, NMI and IRQ5 to IRQ0 are
asynchronous. Changes are detected at
the clock fall when the setup shown is
used. When the setup cannot be used,
detection can be delayed until the next
clock falls. When using as IRL, please
observe the setup time.
2. In the standby mode, tRESPW = tOSC2 (10
ms). In the sleep mode, tRESPW = tPLL1 (100
µs). When the clock multiplication ratio is
changed, tRESPW = tPLL1 (100 µs).
Rev. 5.00 Dec 12, 2005 page xxvi of lxxii