SH7727 Datasheet, PDF (719/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
It depends on setting of SIIER register whether or not an interrupt corresponding to each interrupt
factor is submitted or not depend. SIOF submits each interrupt when interrupt factor that 1 is set to
corresponding bit of SIIER register is set to 1.
(2) Transmit/Receive Interrupt Flag
Transmit or receive interrupt requests INTC or DMAC to accept the interruption through the
interrupt flag, which is generated from the value of TDREQ bit and RDREQ bit in SISTR register.
Table 20.13 shows the setting conditions for the transmit or receive interrupt flag.
Table 20.13 Setting Conditions for the Transmit or Receive Interrupt Flag
Transmit interrupt flag
Setting Conditions
TDREQ in SISTR register = 1
Receive interrupt flag
RDREQ in SISTR register = 1
Resetting Conditions
• TDREQ in SISTR register = 0
• Acknowledge from DMAC
• RDREQ in SISTR register = 0
• Acknowledge from DMAC
(3) Operations in Case of Error
SIOF executes the following operations for the errors which are shown in SISTR as status.
• Transmit FIFO under run (TFUDR): The data that was transmitted directly before is sent
again.
• Transmit FIFO over run (TFOVR): The contents of transmit FIFO is protected, the written data
that became to over flow is ignored.
• Receive FIFO over run (RFOVR): Data that became to over flow is disposed and vanished.
• Receive FIFO under run (RFUDR): Data that is read as final data is output on bus. (indefinite
in specification)
• FS error (FSERR): Internal counter is reset according to the sync. signal that became to error.
Rev. 5.00 Dec 12, 2005 page 647 of 1034
REJ09B0254-0500