SH7727 Datasheet, PDF (275/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
Section 8 User Break Controller
8.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and timing in the
case of instruction fetch.
8.1.1 Features
The UBC has the following features:
• The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and, then channel B match with logical AND, but
not in the same bus cycle).
 Address (Compares 40 bits comprised of a 32-bit logical address prefixed with an ASID
address
Comparison bits are maskable in 32-bit units, user can easily program it to mask addresses
at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc.
The 8-bit ASID checking is from MMU control to indicate hit or not hit.)
One of four address buses (CPU address bus (LAB), cache address bus (IAB),
X-memory address bus (XAB) and Y-memory address bus (YAB)) can be selected.
 Data (only on channel B, 32-bit maskable)
One of the four data buses (CPU data bus (LDB), cache data bus (IDB), X-memory data
bus (XDB) and Y-memory data bus (YDB)) can be selected.
 Bus master: CPU cycle or DMAC cycle
 Bus cycle: instruction fetch or data access
 Read/write
 Operand size: byte, word, or longword
• User break is generated upon satisfying break conditions. A user-designed user-break
condition exception processing routine can be run.
• In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
Rev. 5.00 Dec 12, 2005 page 203 of 1034
REJ09B0254-0500