SH7727 Datasheet, PDF (185/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
MMUCR
31
0
Index
9
0
SV 0 0 RC 0 TF IX AT
Way selection
PTEH register
31
17
VPN
12 10 8
0
VPN 0 ASID
PTEL register
31
10
0
PPN
0 V 0 PR SZ C D SH 0
Write
Ways 0 to 3
Write
0 VPN(31−17) VPN(11−10) ASID(7−) V PPN(31−10) PR(1−0) SZ C D SH
31
Address array
Data array
Figure 3.9 Operation of LDTLB Instruction
3.4.4 Avoiding Synonym Problems
When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of
logical addresses are mapped onto a single physical address, the same physical address data will
be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
The reason why this problem only occurs when using a 1-kbyte page is explained below with
reference to figure 3.10.
To achieve high-speed operation of the SH7727 cache, an index number is created using logical
address bits 11 to 4. When a 4-kbyte page is used, logical address bits 11 to 4 are included in the
offset, and since they are not subject to address translation, they are the same as physical address
bits 11 to 4. In cache-based address comparison and recording in the address array, since the cache
tag address is a physical address, physical address bits 31 to 10 are recorded.
When a 1-kbyte page is used, also, a cache index number is created using logical address bits 11 to
4. However, in case of a 1-kbyte page, logical address bits 11 and 10 are subject to address
translation and therefore may not be the same as physical address bits 11 and 10. Consequently,
Rev. 5.00 Dec 12, 2005 page 113 of 1034
REJ09B0254-0500