SH7727 Datasheet, PDF (645/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit 4: O/E
0
1
Section 19 Serial Communication Interface with FIFO (SCIF)
Description
Even parity.
(Initial value)
If even parity is selected, the parity bit is added to transmit data to make an even
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an even number of 1s in the received character and
parity bit combined.
Odd parity.
If odd parity is selected, the parity bit is added to transmit data to make an odd
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an odd number of 1s in the received character and
parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
0
1
Description
One stop bit.
(Initial value)
In transmitting, a single bit of 1 is added at the end of each transmitted character.
Two stop bits.
In transmitting, two bits of 1 are added at the end of each transmitted character.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and
Pφ/64. For further information on the clock source, bit rate register 2 settings, and baud rate, see
section 19.2.8, Bit Rate Register 2 (SCBRR2).
Bit 1: CKS1 Bit 0: CKS0
0
0
1
1
0
1
Note: Pφ: Peripheral clock
Description
Pφ clock
Pφ/4 clock
Pφ/16 clock
Pφ/64 clock
(Initial value)
Rev. 5.00 Dec 12, 2005 page 573 of 1034
REJ09B0254-0500