SH7727 Datasheet, PDF (641/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.1.4 Register Configuration
Table 19.2 summarizes the SCIF internal registers. These registers specify the data format and bit
rate, and control the transmitter and receiver sections.
Table 19.2 Registers
Register Name
Abbreviation R/W
Initial
Value
Address
Access
Size
Serial mode register 2
SCSMR2
R/W H'00
H'04000150 8 bits
(H'A4000150)^*2
Bit rate register 2
SCBRR2
R/W H'FF
H'04000152 8 bits
(H'A4000152)^*2
Serial control register 2
SCSCR2
R/W H'00
H'04000154 8 bits
(H'A4000154)^*2
Transmit FIFO data register 2 SCFTDR2
Serial status register 2
SCSSR2
W
—
R/(W)^*1 H'0060
H'04000156 8 bits
(H'A4000156)^*2
H'04000158 16 bits
(H'A4000158)^*2
Receive FIFO data register 2
SCFRDR2
R
Undefined H'0400015A 8 bits
(H'A400015A)^*2
FIFO control register 2
SCFCR2
R/W H'00
H'0400015C 8 bits
(H'A400015C)^*2
FIFO data count set register 2 SCFDR2
R
H'0000
H'0400015E 16 bits
(H'A400015E)^*2
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only 0 can be written to clear the flag.
2. When address translation by the MMU does not apply, the address in parentheses
should be used.
Rev. 5.00 Dec 12, 2005 page 569 of 1034
REJ09B0254-0500