SH7727 Datasheet, PDF (989/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 31 User-Debugging Interface (H-UDI)
Table 31.1 shows H-UDI register configuration.
Table 31.1 H-UDI Registers
Name
Abbreviation R/W
CPU Side
Size Address
H-UDI Side _Initial
R/W Size Value*
Instruction register SDIR
R
16 H’04000200 R/W 16 H’FFFF
Device Identification SDID
register
—
—
—
R
32 H’0004200F
Boundary-scan
register
SDBSR
—
—
—
R/W — Undefined
Note: * Initialized when TRST pin is low or when TAP is in the test-logic-reset state.
31.3.1 Bypass Register (SDBPR)
The bypass register (SDBPR) is a 1-bit register that cannot be accessed by the CPU. Setting the
SDIR register to the bypass mode makes the SDBPR register to be connected between the TDI
and TDO H-UDI pins.
31.3.2 Instruction Register (SDIR)
The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its
initial state. It is initialized by TRST or in the TAP test-logic-reset state, and can be written by the
H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is
set to this register.
Bit: 15
14
13
12
11
10
9
8
TI3
TI2
TI1
TI0
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
Bits 15 to 12—Test Instruction Bits (TI3 to TI0): Cannot be written by the CPU.
Rev. 5.00 Dec 12, 2005 page 917 of 1034
REJ09B0254-0500