SH7727 Datasheet, PDF (373/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states
inserted into physical space area 4.
Bit 9: A4W2
0
1
Bit 8: A4W1
0
1
0
1
Bit 7: A4W0
0
1
0
1
0
1
0
1
Description
Inserted Wait State WAIT Pin
0
Ignored
1
Enable
2
Enable
3
Enable
4
Enable
6
Enable
8
Enable
10
Enable (Initial value)
Bits 6 and 5—Area 3 Wait Control (A3W1, A3W0): Specify the number of wait states inserted
into physical space area 3.
• For Ordinary memory
Bit 6: A3W1
0
1
Bit 5: A3W0
0
1
0
1
Description
Inserted Wait States
WAIT Pin
0
Ignored
1
Enable
2
Enable
3
Enable
(Initial value)
• For Synchronous SDRAM
Bit 6: A3W1
0
1
Bit 5: A3W0
0
1
0
1
Description
Synchronous SDRAM: CAS Latency
1
1
2
3
(Initial value)
Rev. 5.00 Dec 12, 2005 page 301 of 1034
REJ09B0254-0500