SH7727 Datasheet, PDF (28/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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949 Figure 32.17 Basic Bus Cycle (External
Wait, WAITSEL = 1)
D31 to D0
(read)
tRDS1
971 Table 32.8 Peripheral Module Signal
Timing
–66.67
Min
Max
Note: * Pcyc stands for “P clock cycle.”
973 Figure 32.42 I/O Port Timing
PORT 7 to 0
(read)
(B:P clock ratio = 1:1)
PORT 7 to 0
(read)
(B:P clock ratio = 1:2)
PORT 7 to 0
(read)
(B:P clock ratio = 1:4)
974
PORT 7 to 0
(write)
Figure 32.45 TCK Input Timing
TCK (input)
1/2_VccQ
t_TCKcyc
t_TCKH
t_TCKL
V_IH V_IH
V_IL V_IL
V_IL
1/2_VccQ
t_TCKf
t_TCKf
Note: When clock is input from TCK pin
Revised Version
Figure 32.19 Basic Bus Cycle (External
Wait, WAITSEL = 1)
D31 to D0
(read)
tRDS1
Note added
Notes: t_RDH1: Specified based on the earliest negate timing of CSn or RD.
t_AH: Specified based on the latest negate timing of CSn, RD, or WEn.
Table 32.11 Peripheral Module Signal
Timing
Min
Max
Note: * Pcyc stands for “peripheral clock
(Pφ) cycle.”
Figure 32.44 I/O Port Timing
PORT A to H,
J to M, SC (read)
(bus clock:peripheral
clock ratio = 1:1)
PORT A to H,
J to M, SC (read)
(bus clock:peripheral
clock ratio = 1:1/2)
PORT A to H,
J to M, SC (read)
(bus clock:peripheral
clock ratio = 1:1/4)
PORT A to H,
J to M, SC (write)
Figure 32.47 TCK Input Timing
TCK (input)
1/2 V_ccQ
t_TCKcyc
t_TCKH
t_TCKL
V_IH V_IH
V_IL V_IL
V_IH
1/2 V_ccQ
t_TCKf
t_TCKf
Rev. 5.00 Dec 12, 2005 page xxviii of lxxii