SH7727 Datasheet, PDF (731/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
21.1.3 Pin Configuration
Table 21.1 shows the pins for AFE interface.
Table 21.1 Pins for AFE Interface
Pin No. Name
I/O
121
AFE_RDET
I
114
AFE_RLYCNT
O
116
AFE_SCLK
I
118
AFE_FS
I
119
AFE_RXIN
I
113
AFE_HC1
O
120
AFE_TXOUT
O
Function
Ringing signal input
On-hook control signal
Shift clock
Frame synchronization signal
Serial receive data
AFE hardware control signal
Serial transmit data
21.1.4 Register Configuration
Table 21.2 shows registers for AFEIF. Byte access registers to these is inhibited.
Table 21.2 AFEIF Registers
Register Name
AFEIF control register 1
AFEIF control register 2
AFEIF status register 1
AFEIF status register 2
Make ratio count register
Minimum pose count register
Dial number queue
Ringing pulse counter
AFE control data register
AFE status data register
Transmit data FIFO port
Receive data FIFO port
Abbre-
viation R/W Initial Value Address
Access
Size
ACTR1 R/W H'0000
H'04000180 16
ACTR2 R/W H'0000
H'04000182 16
ASTR1 R/W H'0F0A
H'04000184 16
ASTR2 R/W H'0300
H'04000186 16
MRCR R/W H'0000
H'04000188 16
MPCR R/W H'0000
H'0400018A 16
DPNQ R/W H'0000
H'0400018C 16
RCNT
R
H'0000
H'0400018E 16
ACDR
R/W H'0000
H'04000190 16
ASDR
R
H'0000
H'04000192 16
TDFP
W
Undetermined H'04000194 32 (16)
RDFP
R
Undetermined H'04000198 32 (16)
Rev. 5.00 Dec 12, 2005 page 659 of 1034
REJ09B0254-0500