SH7727 Datasheet, PDF (172/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
Mapping of the P2 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P2
area, setting the top three logical address bits (bits 31, 30, and 29) to 0 generates the corresponding
physical address. P2 area access cannot be cached.
The P1 and P2 areas are not mapped by the address translation table, so the TLB is not used and
no exceptions like TLB misses occur. Initialization of MMU-related registers, exception handling,
and the like are located in the P1 and P2 areas. Because the P1 area is cached, handlers that require
high-speed processing are placed there.
A part of the control register in the peripheral module is allocated in area 1 of the physical address
space. When the physical address space is not used for address translation, allocate that part of the
control register in the P2 area. When the physical address space is used for address translation, set
no caching.
The P4 area is used for mapping on-chip control register addresses.
In the user mode, 2 Gbytes of the logical address space from H'00000000 to H'7FFFFFFF (area
U0) can be accessed. U0 is mapped onto physical address space in page units, in accordance with
address translation table information. When SR.DSP is off, 2 Gbytes of the logical address space
from H'80000000 to H'FFFFFFFF cannot be accessed in the user mode. Attempting to do so
creates an address error. Write-back or write-through mode can be selected for write accesses by
means of a CCR setting.
When the SR.DSP is on, a new 16-MB address space, Uxy, is defined from address H'A5000000
to H'A5FFFFFF for X/Y RAM. This Uxy space is non-cached, fixed physical address space. Any
access to address space beyond U0 and Uxy creates an address error. For details on the X/Y RAM
space, refer to section 6, X/Y Memory.
Rev. 5.00 Dec 12, 2005 page 100 of 1034
REJ09B0254-0500