SH7727 Datasheet, PDF (231/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 5 Cache
Specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position
within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and
11 is longword 3), W for selecting the way (bits 12 and 11: in normal mode, 00 is way 0, 01 is
way 1, 10 is way 2, and 11 is way 3), and H'F1 to indicate data array access (bits 31 to 24).
Both reading and writing use the longword of the data array specified by the entry address, way
number and longword address. The access size of the data array is fixed at longword.
1. Address array access
Address specification
Read access
31
24
23
14 13 12 11
4
3
2
0
1111 0000
*^{…………}*
W
Entry
0* 0
0
Write access
31
24
23
14 13 12 11
4
3
2
0
1111 0000
*^{…………}*
W
Entry
A* 0
0
Data specification
31 30 29
0 0 0 Address tag (31−10)
10 9
4
LRU
3
2
XX
1
0
UV
2. Data array access (both read and write accesses)
Address specification
31
24
23
14 13 12 11
4
3
21
0
1111 0001
*^{…………}*
W
Entry
L
0
0
Data specification
31
0
Longword
X: 0 for read, don't care for write
*: Don't care bit
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access
Rev. 5.00 Dec 12, 2005 page 159 of 1034
REJ09B0254-0500