SH7727 Datasheet, PDF (650/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 4—Break Detection (BRK): Indicates that a break signal is detected in received data.
Bit 4: BRK
Description
0
No break signal is being received.
(Initial value)
BRK is cleared to 0 when the chip is reset or enters standby mode, or software
reads BRK after it has been set to 1, then writes 0 in BRK.
1
The break signal is received.*
BRK is set to 1 when data including a framing error is received and a framing
error occurs with space 0 in the subsequent received data.
Note: * When a break is detected, transfer of the received data (H'00) to SCFRDR2 stops after
detection. When the break ends and the receive signal becomes mark 1, the transfer of
the received data resumes. The received data of a frame in which a break signal is
detected is transferred to SCFRDR2. After this, however, no received data is transferred
until a break ends with the received signal being mark 1 and the next data is received.
Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO
data register 2 (SCFRDR2).
Bit 3: FER
0
1
Description
No receive framing error occurred in the data read from SCFRDR2. (Initial value)
FER is cleared to 0 when the chip is power-on reset or enters standby mode, or
when no framing error is present in the data read from SCFRDR2.
A receive framing error occurred in the data read from SCFRDR2.
FER is set to 1 when a framing error is present in the data read from SCFRDR2.
Bit 2—Parity Error (PER): Indicates a parity error in the data read from the receive FIFO data
register 2 (SCFRDR2).
Bit 2: PER
0
1
Description
No receive parity error occurred in the data read from SCFRDR2. (Initial value)
PER is cleared to 0 when the chip is power-on reset or enters standby mode, or
when no parity error is present in the data read from SCFRDR2.
A receive parity error occurred in the data read from SCFRDR2.
PER is set to 1 when a parity error is present in the data read from SCFRDR2.
Rev. 5.00 Dec 12, 2005 page 578 of 1034
REJ09B0254-0500