SH7727 Datasheet, PDF (209/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Exception Type
Exception Event
General interrupt requests
Nonmaskable interrupt
H-UDI interrupt
External hardware interrupts:
IRL3 to IRL0 = 0000
IRL3 to IRL0 = 0001
IRL3 to IRL0 = 0010
IRL3 to IRL0 = 0011
IRL3 to IRL0 = 0100
IRL3 to IRL0 = 0101
IRL3 to IRL0 = 0110
IRL3 to IRL0 = 0111
IRL3 to IRL0 = 1000
IRL3 to IRL0 = 1001
IRL3 to IRL0 = 1010
IRL3 to IRL0 = 1011
IRL3 to IRL0 = 1100
IRL3 to IRL0 = 1101
IRL3 to IRL0 = 1110
Note: Exception codes H'120, H'140, and H'3E0 are reserved.
Section 4 Exception Handling
Exception Code
H'1C0
H'5E0
H'200
H'220
H'240
H'260
H'280
H'2A0
H'2C0
H'2E0
H'300
H'320
H'340
H'360
H'380
H'3A0
H'3C0
4.2.5 Exception Request Masks
When the BL bit in SR is 0, exceptions and interrupts are accepted.
If a general exception event occurs when the BL bit in SR is 1, the CPU’s internal registers are set
to their post-reset state, other module registers retain their contents prior to the general exception,
and a branch is made to the same address (H'A0000000) as for a reset.
If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted
until the BL bit is cleared to 0 by software.
For reentrant exception handling, the SPC and SSR must be saved and the BL bit in SR cleared to
0.
Rev. 5.00 Dec 12, 2005 page 137 of 1034
REJ09B0254-0500