SH7727 Datasheet, PDF (253/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
7.3.3 Interrupt Control Register 1 (ICR1)
The ICR1 is a 16-bit register that specifies the detection mode to external interrupt input pins,
IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register, initialized to
H'4000 at power-on reset or manual reset, is not initialized in the standby mode.
Bit: 15
14
13
12
11
10
9
8
MAI IRQLVL BLMSK — IRQ51S IRQ50S IRQ41S IRQ40S
Initial value: 0
1
0
0
0
0
0
0
R/W: R/W R/W R/W
—
R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 15—Mask All Interrupts (MAI): Masks NMI interrupts in standby mode when set to 1. Also
selects whether or not all interrupt requests are masked when a low level is being input to the NMI
pin.
Bit 15: MAI
0
1
Description
All interrupt requests are not masked while NMI pin is receiving low-level input
(Initial value)
All interrupt requests are masked while NMI pin is receiving low-level input
Bit 14—Interrupt Request Level Detect (IRQLVL): Selects whether the IRQ3 to IRQ0 pins are
used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3 to IRL0.
Bit 14: IRQLVL Description
0
Used as four independent interrupt request pins IRQ3 to IRQ0
1
Used as encoded 15-level interrupt pins as IRL3 to IRL0
(Initial value)
Bit 13—BL Bit Mask (BLMSK): Specifies whether NMI interrupts are masked when the BL bit
of the SR register is 1.
Rev. 5.00 Dec 12, 2005 page 181 of 1034
REJ09B0254-0500