SH7727 Datasheet, PDF (259/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
7.3.6 PINT Interrupt Enable Register (PINTER)
The PINTER is a 16-bit read/write register that enables interrupt requests input to external
interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 at power-on reset or
manual reset, but is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT8E
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 0—PINT15 to PINT0 Interrupt Enable (PINT15E to PINT0E): Enable whether the
interrupt requests input to the PINT15 to PINT0 pins.
Bits 15 to 0:
PINT15E to PINT0E
0
1
Description
Disables PINT input interrupt requests
Enables PINT input interrupt requests
(Initial value)
When all or some of these pins, PINT0 to PINT15 are not used as an interrupt input, a bit
corresponding to a pin unused as an interrupt request should be set to 0.
7.3.7 Interrupt Request Register 0 (IRR0)
The IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to
IRQ5 and PINT0 to PINT15. This register is initialized to H'00 at power-on reset or manual reset,
but is not initialized in standby mode.
Bit: 7
6
PINT0R PINT1R
Initial value: 0
0
R/W: R
R
5
IRQ5R
0
R/W
4
IRQ4R
0
R/W
3
IRQ3R
0
R/W
2
IRQ2R
0
R/W
1
IRQ1R
0
R/W
0
IRQ0R
0
R/W
Rev. 5.00 Dec 12, 2005 page 187 of 1034
REJ09B0254-0500