SH7727 Datasheet, PDF (809/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 24 USB HOST Module
24.2.5 HcInterruptEnable
HcInterrutpEnable Register (H'04000410)
Each enable bit in the HcInterruptEnable register corresponds to the related interrupt bit in the
HcInterruptStatus register. The HcInterruptEnable register is used to control an event to generate a
hardware interrupt. A hardware interrupt is requested in the host bus when a bit in the
HcInterruptEnable register is set, a corresponding bit in the HcInteruptEnable register is set, and
the MasterInterrupEnable bit is set. As a result, the USBHI bit in Interrupt Request Register 3
(IRR3) of Interrupt Controller INTC is set (the USBHI bit is used in common regardless of the
content of the interrupt generation event). Therefore, the USBHI bit can be used when an interrupt
generation is detected by HCD.
Writing 1 in this register sets the corresponding bit, while writing 0 leaves the bit. When read, the
current value of this register is returned.
Rev. 5.00 Dec 12, 2005 page 737 of 1034
REJ09B0254-0500