SH7727 Datasheet, PDF (407/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Table 12.13 Relationship between LSI Address Pins and Synchronous DRAM Address Pins
SH7727
Address Pin
A16
A15
A14
A13
A12
RAS Cycle
A24
A23
A22
A21
A20
A11
A19
A10
A18
A9
A17
A8
A16
A7
A15
A6
A14
A5
A13
A4
A12
A3
A11
A2
A10
A1
A9
A0
A0
CAS Cycle
A16
A23
A22
A13
L/H
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDRAM
Address Pin
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Unused
Unused
Function
Address
BANK select bank address
Address
Address precharge
specification
Address
Burst Read: In the example in figure 12.13 it is assumed that four 2M × 8-bit synchronous
DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr
cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2,
and Tc3 cycles, and a READA command in the Tc4 cycle, and the read data is accepted on the
rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is
used to wait for completion of auto-precharge based on the READA command inside the
synchronous DRAM; no new access command can be issued to the same bank during this cycle,
but access to synchronous DRAM for another area is possible. In this LSI, the number of Tpc
cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the
same synchronous DRAM during this interval.
To connect low-speed synchronous DRAM, the cycle can be extended by setting WCR2 and MCR
bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command
output cycle, Tc1, can be specified by the RCD bit in MCR, with a values of 0 to 3 specifying 1 to
4 cycles, respectively. In case of 2 or more cycles, a Trw cycle, in which an NOP command is
Rev. 5.00 Dec 12, 2005 page 335 of 1034
REJ09B0254-0500