SH7727 Datasheet, PDF (288/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7
to ASID0 (BASB7 to BASB0) set in BASRB are masked or not.
Bit 20: BASMB Description
0
All BASRB bits are included in break condition, and ASID is checked
(Initial value)
1
No BASRB bits are included in break condition, and ASID is not checked
Bits 19 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 15—CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the
break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 15:
SCMFCA
0
1
Description
The CPU cycle condition for channel A does not match
The CPU cycle condition for channel A matches
(Initial value)
Bit 14—CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the
break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 14:
SCMFCB
0
1
Description
The CPU cycle condition for channel B does not match
The CPU cycle condition for channel B matches
(Initial value)
Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle
condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 13:
SCMFDA
0
1
Description
The DMAC cycle condition for channel A does not match
The DMAC cycle condition for channel A matches
(Initial value)
Rev. 5.00 Dec 12, 2005 page 216 of 1034
REJ09B0254-0500