SH7727 Datasheet, PDF (680/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.2 Register Description
20.2.1 Mode Register (SIMDR)
This register sets the operating mode of SIOF.
This register is initialized by the power on reset or manual reset.
Bit: 15
14
13
12
11
10
9
8
TRMD1 TRMD0 —
REDG FL3
FL2
FL1
FL0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R*
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
TXDIZ LSBF RCIM
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R*
R*
R*
R*
R*
Note: * 0 must be written into these bits. The operation of this LSI is unpredictable when setting
the value other than 0.
Bits 13 and 4 to 0—Reserved
Bits 15 and 14—Transmit Mode Setting (TRMD1 and TRMD0)
Bit 15: TRMD1 Bit 14: TRMD0 Description
0
0
Slave mode 1
(Initial value)
1
Slave mode 2
1
0
Master mode 1
1
Master mode 2
Note: Refer to section 20.3.3, Transmit Data Format for more details of the functions of each
mode.
Bit 12—Receive with Sampling Edge (REDG): TXD_SIO is output at the opposite edge from
the sampling time of RXD_SIO. (see figure 20.4)
Rev. 5.00 Dec 12, 2005 page 608 of 1034
REJ09B0254-0500