SH7727 Datasheet, PDF (150/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Instruction
Operation
Code
Privileged
Mode
Cycles T Bit
STC.L SR,@–Rn
Rn–4 → Rn, SR → (Rn)
0100nnnn00000011 √
2
—
STC.L GBR,@–Rn
Rn–4 → Rn, GBR → (Rn)
0100nnnn00010011 —
2
—
STC.L VBR,@–Rn
Rn–4 → Rn, VBR → (Rn)
0100nnnn00100011 √
2
—
STC.L SSR,@–Rn
Rn–4 → Rn, SSR → (Rn)
0100nnnn00110011 √
2
—
STC.L SPC,@–Rn
Rn–4 → Rn, SPC → (Rn)
0100nnnn01000011 √
2
—
STC.L R0_BANK,
@–Rn
Rn–4 → Rn, R0_BANK → (Rn) 0100nnnn10000011 √
2
—
STC.L R1_BANK,
@–Rn
Rn–4 → Rn, R1_BANK → (Rn) 0100nnnn10010011 √
2
—
STC.L R2_BANK,
@–Rn
Rn–4 → Rn, R2_BANK → (Rn) 0100nnnn10100011 √
2
—
STC.L R3_BANK,
@–Rn
Rn–4 → Rn, R3_BANK → (Rn) 0100nnnn10110011 √
2
—
STC.L R4_BANK,
@–Rn
Rn–4 → Rn, R4_BANK → (Rn) 0100nnnn11000011 √
2
—
STC.L R5_BANK,
@–Rn
Rn–4 → Rn, R5_BANK → (Rn) 0100nnnn11010011 √
2
—
STC.L R6_BANK,
@–Rn
Rn–4 → Rn, R6_BANK → (Rn) 0100nnnn11100011 √
2
—
STC.L R7_BANK,
@–Rn
Rn–4 → Rn, R7_BANK → (Rn) 0100nnnn11110011 √
2
—
STS MACH,Rn
MACH → Rn
0000nnnn00001010 —
1
—
STS MACL,Rn
MACL → Rn
0000nnnn00011010 —
1
—
STS PR,Rn
PR → Rn
0000nnnn00101010 —
1
—
STS.L MACH,@–Rn Rn–4 → Rn, MACH → (Rn)
0100nnnn00000010 —
1
—
STS.L MACL,@–Rn Rn–4 → Rn, MACL → (Rn)
0100nnnn00010010 —
1
—
STS.L PR,@–Rn
Rn–4 → Rn, PR → (Rn)
0100nnnn00100010 —
1
—
TRAPA #imm
PC → SPC, SR → SSR,
imm << 2 → TRA,
VBR + H'0100 → PC
11000011iiiiiiii —
8
—
Note: * Number of states before the chip enters the sleep state.
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased if there is contention between an instruction
fetch and a data access, or if the destination register of a load instruction (memory →
register) is also used by the following instruction.
Rev. 5.00 Dec 12, 2005 page 78 of 1034
REJ09B0254-0500