SH7727 Datasheet, PDF (290/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Sequence Condition Select (SEQ): Selects two conditions of channels A and B as
independent or sequential.
Bit 3: SEQ
0
1
Description
Channels A and B are compared under the independent condition (Initial value)
Channels A and B are compared under the sequential condition
Bits 2 and 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—The Number of Execution Times Break Enable (ETBE): Enable the execution-times
break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the
number of break conditions matches with the number of execution times that is specified by the
BETR register.
Bit 0: ETBE
0
1
Description
The execution-times break condition is disabled on channel B
The execution-times break condition is enabled on channel B
(Initial value)
8.2.10 Execution Times Break Register (BETR)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
When the execution-times break condition of channel B is enabled, this register specifies the
number of execution times to make the break. The maximum number is 2¹² – 1 times. A power-on
reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A
break is issued when the break condition is satisfied after the BETR becomes H'0001. Bits 15 to
12 are always read as 0 and 0 should always be written in these bits.
Rev. 5.00 Dec 12, 2005 page 218 of 1034
REJ09B0254-0500