SH7727 Datasheet, PDF (683/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
Bit 14—Master Clock Select (MSIMM)
Bit 14: MSIMM
0
1
Description
Use baud rate generator output clock as clock source
Use master clock as clock source
(Initial value)
Bits 13 and 7 to 3—Reserved
Bits 12 to 8—Setting of Prescaler (BRPS4 to BRPS0): The dividing ratio of master clock
(BRPS) is set within the range of 00001 (1/1 times), 00010 (1/2 times), to 11111 (1/31 times) and
00000 (1/32 times: initial value).
Bits 2 to 0—Setting of Dividing Ratio (BRDV2 to BRDV0): Set the dividing ratio of frequency
of output stage (BRDV). Finally, baud rate is decided by the value of BRPS * BRDV (maximum
1/1024).
Bit 2: BRDV2 Bit 1: BRDV1
0
0
1
1
0
Settings other than the above
Bit 0: BRDV0
0
1
0
1
0
Description
1/2 times of prescaler output (Initial value)
1/4 times of prescaler output
1/8 times of prescaler output
1/16 times of prescaler output
1/32 times of prescaler output
(Reserved)
Rev. 5.00 Dec 12, 2005 page 611 of 1034
REJ09B0254-0500