SH7727 Datasheet, PDF (724/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.4 Usage Notes
Note the following when using the SIOF.
For details on using versions previous to the SH7727B please refer to 20.4.1, Notes on Using the
SIOF with Versions Previous to the SH7727B, in addition to the notes below.
1. Using the transmit function in sleep mode
If transmission is enabled when data has already been written to the transmit FIFO, one or two
of the initial data bytes may be lost.
Therefore, data should not be written to the transmit FIFO before enabling transmission.
2. Using control data transmission/reception consecutively on control data interface (secondary
FS position)
The TCRDY value may become 1 before transmit control data is sent, and if the next control
data is written to the control data register at this point, the control data waiting to be sent will
be overwritten and erased.
At this time, also, the control sequence is disrupted and the SIOF switches around the primary
FS and secondary FS, with the result that transmission/reception of data and control data can
no longer be performed normally.
The control data register should therefore be written to after transmit control data has been
sent.
Example:
Reference RCRDY, and write to the control data register when RCRDY is 1.
After transmit control data has been written, it is essential to read the receive control register
(SIRCR) and clear RCRDY.
3. DMA transfer
Do not use 16-byte DMA transfer. (See section 14.3.4, DMA Transfer Types.)
4. Access from the CPU
When performing access from the CPU, do not access the SIOF's transmit/receive FIFO
consecutively, but instead insert an access to somewhere else between SIOF transmit/receive
FIFO accesses.
5. Transmit/receive FIFO underflow
If the transmit/receive FIFO underflows during a transmit/receive operation, control of the
SIOF's transmit/receive FIFO may fail and data may be lost.
To prevent this, either set a watermark so that underflow does not occur, or execute a transmit
reset (TXRST) or receive reset (RXRST) when an empty interrupt is generated.
Rev. 5.00 Dec 12, 2005 page 652 of 1034
REJ09B0254-0500