SH7727 Datasheet, PDF (146/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Shift Instructions
Table 2.23 Shift Instructions
Instruction
ROTL Rn
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAD Rm,Rn
SHAL
SHAR
SHLD
Rn
Rn
Rm,Rn
SHLL Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
Rn ≥ 0: Rn << Rm → Rn
Rn < 0: Rn >> Rm →
[MSB → Rn]
T ← Rn ← 0
MSB → Rn → T
Rn ≥ 0: Rn << Rm → Rn
Rn < 0: Rn >> Rm →
[0 → Rn]
T ← Rn ← 0
0 → Rn → T
Rn << 2 → Rn
Rn >> 2 → Rn
Rn << 8 → Rn
Rn >> 8 → Rn
Rn << 16 → Rn
Rn >> 16 → Rn
Code
0100nnnn00000100
0100nnnn00000101
0100nnnn00100100
0100nnnn00100101
0100nnnnmmmm1100
Privileged
Mode
Cycles T Bit
—
1
MSB
—
1
LSB
—
1
MSB
—
1
LSB
—
1
—
0100nnnn00100000 —
0100nnnn00100001 —
0100nnnnmmmm1101 —
1
MSB
1
LSB
1
—
0100nnnn00000000 —
0100nnnn00000001 —
0100nnnn00001000 —
0100nnnn00001001 —
0100nnnn00011000 —
0100nnnn00011001 —
0100nnnn00101000 —
0100nnnn00101001 —
1
MSB
1
LSB
1
—
1
—
1
—
1
—
1
—
1
—
Rev. 5.00 Dec 12, 2005 page 74 of 1034
REJ09B0254-0500