SH7727 Datasheet, PDF (80/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 1 Overview and Pin Functions
1.2 Block Diagram
SuperH
CPU core
Internal SRAM
(XY RAM)
instruction/data
for CPU/DSP
16 kbytes
DSP core
Memory
management
unit
(MMU)
Cache memory
16 kbytes
Cache access
controller
(CCN)
User
break
controller
(UBC)
Direct
memory access
controller
(DMAC)
CPU bus (L bus)
Interrupt
controller
(INTC)
User
debug
interface
(H-UDI)
Clock
pulse
generator
(CPG)
Bus state
controller
(BSC)
Internal bus (I bus)
Real time
clock
(RTC)
Serial/
smart card
(SCI)
Timer
(TMU)
Internal bus 2 (I2 bus)
Serial
communication
interface
(SCIF)
A/D
converter
(ADC)
D/A
converter
(DAC)
Peripheral bus (P bus)
Peripheral bus
controller
Peripheral bus 1 (P1 bus)
Peripheral bus 2 (P2 bus)
512-byte
SRAM
Analog
front end
interface
(AFEIF)
128-byte
SRAM
Audio
CODEC
interface
(SIOF)
PC card
controller
(PCC)
USB
function
controller
(USBF)
288-byte
SRAM
Li bus
state
controller
(LBSC)
LI bus
2.4-kbyte
line buffer
SRAM
LCD display
controller
(LCDC)
512-byte
pallet SRAM
Figure 1.1 Block Diagram
USB host controller
(USBH)
Rev. 5.00 Dec 12, 2005 page 8 of 1034
REJ09B0254-0500