SH7727 Datasheet, PDF (491/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
• Burst Mode, Level Detection
In the case of burst mode with level detection, the DREQ sampling timing is the same as in the
cycle-steal mode.
For example, as shown in figure 14.22, DMAC transfer begins, at the earliest, three cycles
after the first sampling is performed. The second sampling is started two cycles after the first.
Subsequent sampling operations are performed in the idle cycle following the end of the DMA
transfer cycle.
In the burst mode, also, the DACK output period is the same as that in the cycle-steal mode.
• Burst Mode, Edge Detection
In the case of burst mode with edge detection, DREQ sampling is performed only once.
For example, as shown in figure 14.23, DMAC transfer begins, at the earliest, three cycles
after the first sampling is performed. After this, DMAC transfer is executed continuously until
the number of data transfers set in the DMATCR register have been completed. DREQ is not
sampled during this operation.
To restart DMA transfer after it has been suspended by an NMI, first clear NMIF, then input
an edge request again.
In the burst mode, also, the DACK output period is the same as that in the cycle-steal mode.
Rev. 5.00 Dec 12, 2005 page 419 of 1034
REJ09B0254-0500