SH7727 Datasheet, PDF (121/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
2. Addition index register addressing:
The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy
register is added to each (post-increment).
3. Increment address register addressing:
The Ax and Ay registers are address pointers. After a data transfer, they are each incremented
by 2 (post- increment).
There is an index register for each address pointer. The R8 register is the index register (Ix) for the
X memory address register (Ax), and the R9 register is the index register (Iy) for the Y memory
address register (Ay).
The X and Y data transfer instructions perform word-length processing, and use 16-bit access to
the X/Y data memory. A value of 2 is therefore added to the address register in the increment
processing. To perform decrementing, –2 is set in the index register and addition index register
addressing is specified. In X/Y data addressing, only bits 1 to 15 of the address pointer are valid.
When using X/Y data addressing, 0 must always be written to bit 0 of the address pointer and
index register.
X/Y data transfer addressing is shown in figure 2.12. When accessing X and Y memory using the
X and Y buses, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of
@AY+ or @Ay + Iy is stored in the lower word of Ay, while the upper word retains its original
value.
R8[Ix]
+2 (INC)
+0 (no update)
R4[Ax]
R5[Ax]
ALU
R9[Iy]
+2 (INC)
+0 (no update)
R6[Ay]
R7[Ay]
AU
Note: Three address processing methods:
1. Increment
2. Index register addition (Ix/Iy)
3. No increment
AU: Adder provided
for DSP addressing
Post-updating is used in all cases.
The address pointer can be decremented by setting −2/−4 in the index register.
Figure 2.12 X and Y Data Transfer Addressing
Rev. 5.00 Dec 12, 2005 page 49 of 1034
REJ09B0254-0500