SH7727 Datasheet, PDF (353/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 11 Extend Clock Pulse Generator for USB (EXCPG)
Bits 5 to 3—Clock Select (USBCKSEL2 to USBCKSEL0): Selects the clock source. Although
initialized as peripheral clock (Pφ) after power on reset, the value of USBCKSEL must be changed
to adequate value to generate 48 MHz. To prevent malfunction, the USB Host and USB Function
must be set in module standby state or module reset state when the value of USBCKSEL is
changed.
Bits 5 to 3
000
100
101
110
Another value
Function (Clock Selection)
Peripheral Clock (Pφ)
Internal Clock (Iφ)
Bus Clock (Bφ)
External clock (UCLK)
Reserved (setting prohibited)
(Initial value)
Bits 2 to 0—Divider Select (USBDIVSEL2 to USBDIVSEL0): Selects the dividing ratio of
clock source to generate USB clock so that the USB clock is 48 MHz.
Bits 2 to 0
Function (Dividing Ratio Selection)
000
1/1
(Initial value)
001
1/2
010
1/3
1**
Internal clock (Iφ), bus clock (Bφ), external clock (UCLK) halted
Note: To reduce power consumption, set USBDIVSEL2 to 1 and halts internal clock (Iφ), bus clock
(Bφ), or external clock (UCLK) input.
11.4 Usage Notes
By selecting LCLK (LCD clock)/UCLK (USB clock) as the function of the LCLK/UCLK/PTD[6]
pin, it is possible to supply the clock input to the pin to both the LCD controller and the USB
function controller.
However, in this case it is necessary, using the divider select bit (USBDIVSEL[2:0]) in
EXCPGCR (EXCPG control register), to set the USB clock so that the final clock frequency is
48 MHz. This means that the input clock frequency will be 48 MHz. If this frequency is not
suitable as the operating clock for the LCD controller, consider selecting an internal clock for
LCLK. In addition, it may be impossible to maintain the accuracy of the USB standard clock
because the CPU clock (Iφ) and bus clock (Bφ) are generated by the internal PLL of the SH7727
by frequency multiplication. Therefore, it is recommended that a dedicated 48 MHz external clock
be input to UCLK to ensure the accuracy of the USB standard clock.
Rev. 5.00 Dec 12, 2005 page 281 of 1034
REJ09B0254-0500