SH7727 Datasheet, PDF (69/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 18 Smart Card Interface
Table 18.1 SCI Pins 545
Table 18.2 Registers 545
Table 18.3 Register Settings for the Smart Card Interface ....................................................... 551
Table 18.4 Relationship of n to CKS1 and CKS0 .................................................................... 553
Table 18.5 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0).................................. 553
Table 18.6 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0).................................. 553
Table 18.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)....................... 554
Table 18.8 Register Set Values and SCK Pin........................................................................... 554
Table 18.9 Smart Card Mode Operating State and Interrupt Sources ...................................... 561
Section 19 Serial Communication Interface with FIFO (SCIF)
Table 19.1 SCIF Pins................................................................................................................ 568
Table 19.2 Registers 569
Table 19.3 SCSMR2 Settings................................................................................................... 581
Table 19.4 Bit Rates and SCBRR2 Settings............................................................................. 581
Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)............................................................................................ 585
Table 19.6 SCSMR2 Settings and SCIF Transmit/Receive ..................................................... 589
Table 19.7 Settings for SCSMR2 and SCSCR2 and Selection of Clock Source of SCIF ........ 590
Table 19.8 Serial Transmit/Receive Formats ........................................................................... 590
Table 19.9 SCIF Interrupt Sources........................................................................................... 600
Section 20 Serial IO (SIOF)
Table 20.1 SIOF Pin List.......................................................................................................... 607
Table 20.2 SIOF Register Configuration.................................................................................. 607
Table 20.3 Examples of SIOF Clock Frequency ...................................................................... 630
Table 20.4 Serial Transmit Mode............................................................................................. 632
Table 20.5 Frame Length ......................................................................................................... 633
Table 20.6 Transmit Data Sound Mode ................................................................................... 635
Table 20.7 Receive Data Sound Mode ..................................................................................... 635
Table 20.8 Control Data Channel Number Establishment ....................................................... 636
Table 20.9 Transmit Request Submit Condition ...................................................................... 639
Table 20.10 Receive Request Submit Condition........................................................................ 640
Table 20.11 Transmit or Receive Reset...................................................................................... 645
Table 20.12 SIOF Interrupt Factors............................................................................................ 646
Table 20.13 Setting Conditions for the Transmit or Receive Interrupt Flag .............................. 647
Section 21 Analog Front End Interface (AFEIF)
Table 21.1 Pins for AFE Interface............................................................................................ 659
Rev. 5.00 Dec 12, 2005 page lxix of lxxii