SH7727 Datasheet, PDF (421/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Section 12 Bus State Controller (BSC)
T1 TB2 TB1 TB2 TB1 TB2 TB1 T2
A25 to A4
A3 to A0
CSn
RD/WE
RD
D31 to D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 12.23 Burst ROM Basic Access Timing
Rev. 5.00 Dec 12, 2005 page 349 of 1034
REJ09B0254-0500