SH7727 Datasheet, PDF (442/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
13.1.4 Bus Control Register 2 (BCR2)
The bus control register 2 (BCR2) is a 16-bit read/write register that sets the bus-size width of
each area and selects whether an 8-bit port is used or not. It is initialized to H'3FF0 by a power-on
reset, but is not initialized by a manual reset or by standby mode. Do not access external memory
outside area 0 until BCR2 register initialization is complete.
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
10
9
8
— A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0
0
1
1
1
1
1
1
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
A3SZ1 A3SZ0 A2SZ1 A2SZ0 —
—
—
—
Initial value: 1
1
1
1
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R
R
R
R
Bits 15 to 8 and 5 to 0 —Not referenced
Bits 7 and 6—Area 3 Bus Size Specification (A3SZ1, A3SZ0): Specifies the bus sizes of
physical space area 3.
Bit 7: A3SZ1
0
1
0
1
Bit 6: A3SZ0
0
1
0
1
0
1
0
1
Port A/B
Unused
Used
Description
Reserved (Setting disabled)
Reserved (Setting disabled)
16-bit bus width
32-bit bus width
Reserved (Setting disabled)
Reserved (Setting disabled)
16-bit bus width
Reserved (Setting disabled)
Rev. 5.00 Dec 12, 2005 page 370 of 1034
REJ09B0254-0500