SH7727 Datasheet, PDF (243/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Interrupt
request
Section 7 Interrupt Controller (INTC)
SH7727
Priority
encoder
4
IRL3 to IRL0
IRL3 to IRL0
Figure 7.2 Example of IRL Interrupt Connection
Table 7.3 IRL3 to IRL0 Pins and Interrupt Levels
IRL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IRL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IRL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IRL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that
no transient level on the IRL pin change is detected. In the standby mode, as the peripheral clock
is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead. Therefore
Rev. 5.00 Dec 12, 2005 page 171 of 1034
REJ09B0254-0500