SH7727 Datasheet, PDF (346/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 10 On-Chip Oscillation Circuits
Bit 4—Watchdog Timer Overflow (WOVF): Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval timer mode.
Bit 4: WOVF
0
1
Description
No overflow
WTCNT has overflowed in watchdog timer mode
(Initial value)
Bit 3—Interval Timer Overflow (IOVF): Indicates that the WTCNT has overflowed in interval
timer mode. This bit is not set in watchdog timer mode.
Bit 3: IOVF
0
1
Description
No overflow
WTCNT has overflowed in interval timer mode
(Initial value)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock to be used for the
WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow
period in the table is the value when the peripheral clock (Pφ) is 15 MHz.
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio
Overflow Period
(when Pφ = 15 MHz)
0
0
0
1
(Initial value)
17 µs
1
1/4
68 µs
1
0
1/16
273 µs
1
1/32
546 µs
1
0
0
1/64
1.09 ms
1
1/256
4.36 ms
1
0
1/1024
17.48 ms
1
1/4096
69.91 ms
Note: If bits CKS2 to CKS0 are modified when the WDT is running, the up-count may not be
performed correctly. Ensure that these bits are modified only when the WDT is not running.
Rev. 5.00 Dec 12, 2005 page 274 of 1034
REJ09B0254-0500