SH7727 Datasheet, PDF (578/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Table 17.5 Bit Rates and SCBRR Settings in Clock Synchronous Mode
Pφ (MHz)
Bit Rate
(bits/s)
4
n
N
8
n
N
16
n
N
28.7
n
N
30
n
N
110
——
——
——
——
——
250
2
249
3
124
3
249
——
——
500
2
124
2
249
3
124
3
223
3
233
1k
1
249
2
124
2
249
3
111
3
116
2.5k
1
99
1
199
2
99
2
178
2
187
5k
0
199
1
99
1
199
2
89
2
93
10k
0
99
0
199
1
99
1
178
1
187
25k
0
39
0
79
0
159
1
71
1
74
50k
0
19
0
39
0
79
0
143
0
149
100k
0
9
0
19
0
39
0
71
0
74
250k
0
3
0
7
0
15
——
0
29
500k
0
1
0
3
0
7
——
0
14
1M
0
0*
0
1
0
3
——
——
2M
0
0*
0
1
——
——
Notes: Settings with an error of 1% or less are recommended.
Blank: No setting possible
—: Setting possible, but error occurs. (Refer to section 17.2.9, Bit Rate Register
(SCBRR))
*:
Continuous transmit/receive not possible as transfer capability to the buffer
becomes insufficient.
Rev. 5.00 Dec 12, 2005 page 506 of 1034
REJ09B0254-0500