SH7727 Datasheet, PDF (439/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
Section 13 Li Bus State Controller (LBSC)
13.1 Overview
The Li bus state controller (LBSC) functions enable LCD controller and Open HCI compliant
USB Host controller to link directly with synchronous DRAM. LBSC is a slave bus state
controller of BSC.
13.1.1 Features
The LBSC has the following features:
• Direct interface to synchronous DRAM
 Physical address space is specified only to area 3
 A maximum 64 Mbytes
 Multiplexes row/column addresses according to synchronous DRAM capacity
 Supports burst operation with various burst length; selectable from 1 to 32
 Controls timing of synchronous DRAM direct-connection control signals according to
register setting
 16-bit or 32-bit bus width according to register setting
13.1.2 Register Configuration
The LBSC does not have any register inside, but refers BSC registers shown in table 13.1.
Table 13.1 Register Configuration
Name
Abbr. R/W
Bus control register 1
BCR1 R/W
Bus control register 2
BCR2 R/W
Wait state control register 1 WCR1 R/W
Wait state control register 2 WCR2 R/W
Individual memory control
register
MCR
R/W
Note: * Initialized by power-on resets.
Initial Value*
H'0000
H'3FF0
H'3FF3
H'FFFF
H'0000
Address
H'FFFFFF60
H'FFFFFF62
H'FFFFFF64
H'FFFFFF66
H'FFFFFF68
Bus Width
16
16
16
16
16
Rev. 5.00 Dec 12, 2005 page 367 of 1034
REJ09B0254-0500