SH7727 Datasheet, PDF (674/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
5. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop
bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the
TEND flag has been confirmed, the stop bit will be in the process of transmission and will not
be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial
clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is
confirmed.
6. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a
frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the
fall of the start bit, which it samples on the base clock. Receive data is latched at the rising
edge of the eighth base clock pulse. The timing is shown in figure 19.12.
Base clock
Receive
data (RxD2)
Synchro-
nization
sampling
timing
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
−7.5 clocks +7.5 clocks
Start bit
D0
D1
Data
sampling
timing
Figure 19.12 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation
(1).
Equation 1:
M = 0.5 − ¹ − (L − 0.5) F − ^{D − 0.5} (1 + F) × 100% ^{........................ (1)}
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
Rev. 5.00 Dec 12, 2005 page 602 of 1034
REJ09B0254-0500