SH7727 Datasheet, PDF (272/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Table 7.8 Interrupt Response Time
Item
Time for priority
decision and SR mask
bit comparison
Wait time until end of
sequence being
executed by CPU
Time from interrupt
exception handling
(save of SR and PC)
until fetch of first
instruction of
exception handler is
started
Number of States
Peripheral
NMI
IRQ
PINT
Modules
Notes
0.5 × Icyc
+ 0.5 × Bcyc
+ 0.5 × Pcyc
0.5 × Icyc
0.5 × Icyc
+ 1 × Bcyc + 3.5 × Pcyc
+ 4.5 × Pcyc^*4
0.5 × Icyc
+ 1.5 × Pcyc^*5
0.5 × Icyc
+ 3 × Pcyc^*6
X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc
Interrupt exception
handling is kept
waiting until the
executing instruction
ends. If the number of
instruction execution
states is S^*1, the
maximum wait time is:
X = S – 1.
However, if BL is set to
1 by instruction
execution or by an
exception, interrupt
exception handling is
deferred until
completion of an
instruction that clears
BL to 0. If the following
instruction masks
interrupt exception
handling, the
processing may be
further deferred.
5 × Icyc
5 × Icyc
5 × Icyc
5 × Icyc
Rev. 5.00 Dec 12, 2005 page 200 of 1034
REJ09B0254-0500