SH7727 Datasheet, PDF (147/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Branch Instructions
Table 2.24 Branch Instructions
Instruction
Operation
Code
BF
label
If T = 0, disp × 2 + PC → PC; 10001011dddddddd
if T = 1, nop (where label is
disp + PC)
BF/S label
Delayed branch, if T = 0,
disp × 2 + PC → PC;
if T = 1, nop
10001111dddddddd
BT
label
Delayed branch, if T = 1,
disp × 2 + PC → PC;
if T = 0, nop
10001001dddddddd
BT/S label
If T = 1, disp × 2 + PC → PC;
if T = 0, nop
10001101dddddddd
BRA label
Delayed branch,
disp × 2 + PC → PC
1010dddddddddddd
BRAF Rm
Delayed branch,
Rm + PC → PC
0000mmmm00100011
BSR label
Delayed branch, PC → PR,
disp × 2 + PC → PC
1011dddddddddddd
BSRF Rm
Delayed branch, PC → PR,
Rm + PC → PC
0000mmmm00000011
JMP @Rm
Delayed branch, Rm → PC
0100mmmm00101011
JSR @Rm
Delayed branch, PC → PR,
Rm → PC
0100mmmm00001011
RTS
Delayed branch, PR → PC
0000000000001011
Note: * One state when the branch is not executed.
Section 2 CPU
Privileged
Mode
Cycles T Bit
—
3/1*
—
—
2/1*
—
—
3/1*
—
—
2/1*
—
—
2
—
—
2
—
—
2
—
—
2
—
—
2
—
—
2
—
—
2
—
Rev. 5.00 Dec 12, 2005 page 75 of 1034
REJ09B0254-0500