SH7727 Datasheet, PDF (128/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Instruction Format
nm type
15
0
xxxx nnnn mmmm xxxx
md type
15
0
xxxx xxxx mmmm dddd
nd4 type
15
0
xxxx xxxx nnnn dddd
nmd type
15
0
xxxx nnnn mmmm dddd
Source
Operand
Destination
Operand
Sample Instruction
mmmm: register
direct
nnnn: register
direct
ADD Rm,Rn
mmmm: register
indirect
nnnn: register
indirect
MOV.L Rm,@Rn
mmmm: post-
MACH, MACL
increment register
indirect (multiply-
and-accumulate
operation)
MAC.W @Rm+,@Rn+
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
mmmm: post-
increment
register indirect
nnnn: register
direct
MOV.L @Rm+,Rn
mmmm: register
direct
nnnn: pre-
MOV.L Rm,@-Rn
decrement register
indirect
mmmm: register
direct
nnnn: indexed
register indirect
MOV.L Rm,@(R0,Rn)
mmmmdddd:
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
R0 (register
direct)
nnnndddd:
MOV.B R0,@(disp,Rn)
register indirect
with displacement
mmmm: register
direct
nnnndddd:
MOV.L Rm,@(disp,Rn)
register indirect
with displacement
mmmmdddd:
nnnn: register
register indirect direct
with displacement
MOV.L @(disp,Rm),Rn
Rev. 5.00 Dec 12, 2005 page 56 of 1034
REJ09B0254-0500