SH7727 Datasheet, PDF (567/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
17.2.7 Serial Status Register (SCSSR)
Bit:
7
6
5
4
3
TDRE RDRF ORER FER PER
Initial value:
1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * The only value that can be written is a 0 to clear the flag.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate SCI operating state.
The CPU can always read and write the SCSSR, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
The SCSSR is initialized to H'84 by a reset or in standby and module standby modes.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the SCTDR into the SCTSR and new serial transmit data can be written in the SCTDR.
Bit 7: TDRE
0
1
Description
SCTDR contains valid transmit data
[Clear condition]
When software reads TDRE after it has been set to 1, then writes 0 in TDRE or
data is written in SCTDR.
SCTDR does not contain valid transmit data
(Initial value)
[Setting conditions]
1. When the chip is reset or enters standby mode
2. When the TE bit in the serial control register (SCSCR) is cleared to 0
3. When SCTDR contents are loaded into SCTSR, so new data can be written
in SCTDR.
Rev. 5.00 Dec 12, 2005 page 495 of 1034
REJ09B0254-0500