SH7727 Datasheet, PDF (76/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 1 Overview and Pin Functions
Item
Memory
management
unit (MMU)
Features
• 4 Gbytes of address space, 256 address spaces (ASID 8 bits)
• Page unit sharing
• Supports multiple page sizes: 1 kbytes or 4 kbytes
• 128-entry, 4-way set associative TLB
• Supports software selection of replacement method and random-
replacement algorithms
• Contents of TLB can directly be accessed according to the address mapping
Cache memory
• 16-kbyte cache, mixed instruction/data
• 256 entries, 4-way set associative, 16-byte block length
• Write-back, write-through, least recently used (LRU) replacement algorithm
• 1-stage write-back buffer
• Maximum 2 ways of the cache can be locked
X/Y memory
• User-selectable mapping mechanism
 Fixed mapping for mission-critical realtime applications
 Automatic mapping through TLB for easy to use
• 3 independent read/write ports
 8-/16-/32-bit access from the CPU
 Maximum two 16-bit accesses from the DSP
 8-/16-/32-bit access from the DMAC
• 8-kbyte RAM for X and Y memory individually
Interrupt
• 7 external interrupt pins (NMI, IRQ5–IRQ0)
controller (INTC) _{• On-chip peripheral interrupts: set priority levels for each module}
User break
• 2 break channels
controller (UBC) _{• Addresses, data values, type of access, and data size can all be set as}
break conditions
• Supports a sequential break function
Rev. 5.00 Dec 12, 2005 page 4 of 1034
REJ09B0254-0500