SH7727 Datasheet, PDF (316/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
Table 9.4 Register States in Standby Mode
Module
Registers Initialized
Interrupt controller (INTC)
—
On-chip clock pulse generator
—
(OSC)
User break controller (UBC)
—
Bus state controller (BSC)
—
Timer unit (TMU)
TSTR register
Realtime clock (RTC)
—
A/D converter (ADC)
All registers
D/A converter (DAC)
—
Li bus state controller (LBSC)
—
LCD controller (LCDC)
—
USB host controller (USBH)
—
USB function module (USBF)
—
AFE interface (AFEIF)
—
Serial IO with FIFO (SIOF)
—
PC card controller (PPC)
—
Note: * PCC0ISR reflects the normal status.
Registers Retaining Data
All registers
All registers
All registers
All registers
Registers other than TSTR
All registers
—
All registers
All registers
All registers
All registers
All registers
All registers
All registers
Registers other than PCC0ISR*
The procedure for moving to standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT.
Set the WDT’s timer counter (WTCNT) to 0 and set a value to the CKS2 to CKS0 bits in the
WTCSR register to secure the specified oscillation settling time.
2. After the STBY bit in the STBCR register is set to 1, the SLEEP instruction is executed.
3. When the chip enters standby mode and the clocks within the chip are halted, he STATUS1
pin output goes low and the STATUS0 pin output goes high.
Rev. 5.00 Dec 12, 2005 page 244 of 1034
REJ09B0254-0500