SH7727 Datasheet, PDF (483/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
CK
A25 to A0
Transfer source Transfer source
address (H)
address (L)
NOP
Indirect address
Transfer desti-
nation address
CSn
D31 to D0
Internal
address bus
Internal data
bus
DMAC indirect
address buffer
DMAC data
buffer
Indirect
address (H)
Indirect
address (L)
Transfer source
address^*1
NOP
Indirect
address
Transfer
data
Transfer
data
Transfer source
address^*2
Transfer data
Transfer
data
Indirect address
Transfer data
RD
WEn
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
(3rd)
Data
write cycle
(4th)
Notes: 1. The internal address bus value does not change, and controlled by the port.
2. The DMAC does not fetch the value until 32-bit data is output to the internal
data bus.
Transfer between external memories (external memories is 16-bit bus width)
Figure 14.10 Example of Transfer Timing in Indirect Address Mode
(Transfer between External Memories, External Memory with 16-bit Width)
Rev. 5.00 Dec 12, 2005 page 411 of 1034
REJ09B0254-0500