SH7727 Datasheet, PDF (652/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Upper 8 bits:
Initial value:
R/W:
15
PER3
0
R
14
PER2
0
R
13
PER1
0
R
12
PER0
0
R
11
FER3
0
R
10
FER2
0
R
9
FER1
0
R
8
FER0
0
R
Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicates the quantity of data
including a parity error in the received data stored in the receive FIFO data register 2 (SCFRDR2).
The value indicated by the bits 15 to 12 represents the number of parity errors in SCFRDR2.
Bits 11 to 8—Number of Framing Errors 3 to 0 (FER3 to FER0): Indicates the quantity of data
including a framing error in the received data stored in SCFRDR2. The value indicated by bits 11
to 8 represents the number of framing errors in SCFRDR2.
19.2.8 Bit Rate Register 2 (SCBRR2)
The bit rate register 2 (SCBRR2) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in the serial mode register 2 (SCSMR2),
determines the serial transmit/receive bit rate.
The CPU can always read and write the SCBRR2. The SCBRR2 is initialized to H'FF by a reset or
in module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The SCBRR2 setting is calculated as follows:
Asynchronous mode:
N=
Pφ
64 × 2^2n–1 × B
× 10⁶ – 1
B: Bit rate (bit/s)
N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 19.3.)
Rev. 5.00 Dec 12, 2005 page 580 of 1034
REJ09B0254-0500